Example FIGS. 1A to 1D are cross sectional views explaining a related method of manufacturing a MIM (metal-insulator-metal) capacitor of a semiconductor device. As shown in example FIG. 1A, a lower metal film (lower capacitor electrode) 11, an insulator film 12 and an upper metal film (upper capacitor electrode) 13 are sequentially formed over a semiconductor substrate 1. Then, as shown in example FIG. 1B, a photoresist material is coated onto the upper metal film (upper capacitor electrode) 13, and the coated photoresist material is patterned so as to form a first photoresist pattern 14.
By performing an etching process using the first photoresist pattern 14 as a mask, the upper metal film 13 and the insulator film 12 are etched selectively. Through the selective etching process, an upper metal film pattern (upper capacitor electrode) 13a and an insulator film pattern 12a are formed, thereby completing an MIM (metal-insulator-metal) capacitor.
As shown in example FIG. 1C, etching and cleaning steps are performed to remove the first photoresist pattern 14. After that, a dielectric film 16 is formed over an entire surface of the semiconductor substrate 1 including the upper metal film pattern 13a. To form contact holes 18 in the dielectric film 16, a photoresist material is coated and patterned, thereby forming a second photoresist pattern 17. Through an etching process using the second photoresist pattern 17 as a mask, the dielectric film 16 is etched selectively, thereby forming the contact holes 18 to open predetermined portions of the lower metal film 11 and the upper metal film 13a. 
After removing the second photoresist pattern 17 by etching and cleaning, as shown in example FIG. 1D, a conductive film is deposited over the dielectric film pattern 16 so that the contact holes 18 are filled by the conductive film. Plugs 19, formed by the conductive film, are in contact with the lower metal film 11 and the upper metal film pattern 13a. After that, a metal film is deposited over the dielectric film pattern 16. The deposited metal film is patterned to thereby form metal electrodes 20 which contact the plugs 19. A nitride film is deposited over the metal electrodes 20 and selectively patterned, thereby forming a nitride film pattern 21 with openings for the metal electrodes 20.
The semiconductor device manufactured by the aforementioned method may have a problem of step coverage between an MIM capacitor region and its circumferential region. The problem may occur when depositing the dielectric film 16, due to the thickness of the insulator film 12a and the upper metal film (upper capacitor electrode) 13a included in the MIM capacitor. Due to the step coverage between the MIM capacitor region and its circumferential region, a DOF (Depth of Focus) margin becomes insufficient, creating a problem of an imprecise pattern. Also, an entirely uneven surface of a wafer causes a limitation in flatness achievable in a chemical mechanical polishing (CMP) process.